The disclosure relates to low drop-out regulators, and in particular, to ultra low power low drop-out regulators.
Unless otherwise indicated herein, the approaches described in this section are not admitted to be prior art by inclusion in this section.
Existing high load current rating low-dropout regulators (LDOs) have about a 10 microamp quiescent current even in a low power mode. There are typically tens of LDOs in a power management integrated circuit (PMIC) that in total contribute to a significant portion of the quiescent current of the PMIC. For the next generation chipsets, it is desired that these LDOs have a reduced quiescent current down to a 1 microamp level when the load is in a retention mode (of a memory, for example) or a sleep mode.